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In this post we highlight the Powerful Applications of Vedic Mathematics in the field of Information Technology. We bring to light for the first time the works and papers of students who have used Vedic Math in fields of Digital Signal Processing (DSP), Chip Designing, Discrete Fourier Transform (DFT), High Speed Low Power VLSI Arithmetic and Algorithms,RSA Encryption System etc. All the papers presented here on various IT topics have used the Vedic Math Methods such as Multiplication, Division, Squares, Cubes some even claim to have used Geometry and Calculus in their programming structure.

The first set of Papers is by Himanshu Thapiyal who is foremost leader in implementing the Vedic Math sutras to the use of Information Technology.Himanshu Thapliyal received his B.Tech in Computer Engineering in 2004 from G.B. Pant University of Agril. & Technology, Pantnagar, India.Currently,he is doing MS by research under Dr. M.B Srinivas(Head),Centre for VLSI & Embedded System Technologies, International Institute of Information Technology, Hyderabad, India. He has participated in various International and National conferences and workshops. He has published nearly 40 research papers in reviewed International Conferences and Journals. He was awarded 1 lakh rupees by the State Government of Uttaranchal for his research on Vedic Mathematics, and for the participation in conferences in USA & UK.He has also worked with Dr. Hamid R.Arabnia, University of Georgia, U.S.A.Currently, he is also working with Dr. Mark Zwolinski,University of Soutampton, U.K. His website can be found at These Papers have been presented at various conferences around the world organised by NASA, Various Security Companies, IBM, Intel etc. Links to specific pages on these organization’s websites can be requested for further study. 1) VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics by Himanshu Thapliyal This paper proposes the hardware implementation of RSA encryption/decryption algorithm using the algorithms of Ancient Indian Vedic Mathematics that have been modified to improve performance. The recently proposed hierarchical overlay multiplier architecture is used in the RSA circuitry for multiplication operation. The most significant aspect of the paper is the development of a division architecture based on Straight Division algorithm of Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency.The coding is done in Verilog HDL and the FPGA synthesis is done using Xilinx Spartan library. The results show that RSA circuitry implemented using Vedic division and multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplication and division architectures. www.vedicmathsindia.org/Vedic Math IT/1.VLSI Implementation of RSA encryption system using Vedic Math.pdf
2) Time-Area- Power Efficient Multiplier and Square Architecture Based On Ancient Indian Vedic Mathematics by Himanshu Thapliyal and Hamid R.Arabnia
In this paper new multiplier and square architecture is proposed based on algorithm ancient Indian Vedic Mathematics, for low power and high speed applications. It is base on generating all partial products and their sums in one step. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopys FPGA Express using: Xilinx,Family: Spartan Svq300, Speed Grade: -6. The present paper relates to the field of math coprocessors in computers and more specifically to improvement in speed and power over multiplication and square algorithm implemented in coprocessors. In FPGA implementation it has been found that the proposed Vedic multiplier and square are faster than array multiplier and Booth multiplier. www.vedicmathsindia.org/Vedic Math IT/2.Square Architecture Using Vedic Math.pdf 3) A High Speed and Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics by Himanshu Thapliyal and M.B.Srinivas Abstract—This paper presents for point doubling using square algorithms of Ancient Indian Vedic Mathematics. In order to calefficient hardware circuitry culate the square of a number, “Duplex” D property of binary numbers is proposed. A technique for computation of fourth power of a number is also being proposed. A considerable improvement in the point additions and doubling has been observed when implemented using proposed techniques for exponentiation. www.vedicmathsindia.org/Vedic Math IT/3.Elliptic Curve Encryption Using Vedic Math.pdf
The Next Paper is by Prof. Purushottam Chidgupkar and Prof.Mangesh Karad on Digital Signal Processing ( DSP). It has been published in the Global Journal of Engineering Education. Prof. Purushottam D.Chidgupkar, Ex-Commander of the Indian Navy and postgraduate from Cranfield University, UK, has been at the MIT campus since January 1998. He has made noteworthy contributions in the development of one of thebest IT infrastructure at the MIT Women Engineering College, Maharahstra Academy of Engineering and Educational Research, Pune, India. His own specialisation is in the area of digital signal processing (DSP) and has, to his credit, quite a few research projects completed under his close guidance. He has also been exploring Vedic mathematics concepts for their usability in DSP. His research thus far has given ample evidence of the better efficiency of Vedic algorithms and their implementation in computers with reduced processing times. He intends to design separate processor architecture suitable for Vedic approaches and achieve further improvements in processing time. 4) The Implementation of Vedic Algorithms in Digital Signal Processing by Purushottam D. Chidgupkar and Mangesh T. Karad Digital signal processing (DSP) is the technology that is omnipresent in almost every Engineering discipline. It is also the fastest growing technology this century and, therefore, it poses tremendous challenges to the engineering community. Faster additions and multiplications are of extreme importance in DSP for convolution, discrete Fourier transforms digital filters, etc. The core computing process is always a multiplication routine; therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them. Vedic mathematics is the name given mto the ancient system of mathematics, which was rediscovered, from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. As such, the methods are complementary, direct and easy. The authors highlight the use of multiplication process based on Vedic algorithms and its implementations on 8085 and 8086 microprocessors, resulting in appreciable savings in processing time. The exploration of Vedic algorithms in the DSP domain may prove to be extremely advantageous. Engineering institutions now seek to incorporate research-based studies in Vedic mathematics for its applications in various engineering processes. Further research prospects may include the design and development of a Vedic DSP chip using VLSI technology. www.vedicmathsindia.org/Vedic Math IT/4.Digital Signal Processing by Chidgupar.pdf The Next set of Papers is by Talented Young Engineering and Computer Students. Shripad Kulkarni is pursuing the Master of Engineering in Process Instrumentation. He has correlated one process in Digital Signal Processing and compared it with the Vertically and Crosswise process of Vedic maths. Also done analysis tried to show how number of multiplication and additions reduce time and process. 5) Discrete Fourier Transform (DFT) by using Vedic Mathematics by Shripad Kulkarni. Though there are many algorithms for the same task only VAN-NEUMAN architectural implementation of classical method is found to be used in present day digital computers. The Vedic mathematical methods suggested by Shankaracharya Sri. Bharti Krishna Tirthaji through his book offer efficient alternatives. The present seminar analyses and compares the implementation of DFT algorithm by existing and by Vedic mathematical technique . It is suggested that architectural level changes in the entire computation system to accommodate the Vedic mathematical method shall increase the overall efficiency of DFT procedure. https://vedicmathsindia.org/Vedic Math IT/5.DFT Using Vedic Math Kulkarni.pdf 6) Kunal Singh and Vinesh Raicha are pursuing Masters of Science in Computer Science and their partner Rohit Jog who is also an MSc in Computer Science is currently working with Symantec.They show some Vedic Math Algorithm Applications in their Paper and show other useful application of Vedic Math in the field of IT with their diagrams. www.vedicmathsindia.org/Vedic Math IT/6. Vedic Algorithms.pdf
All Papers are Copyrighted to their respective authors.Please Add to comments for your feedback.


11 COMMENTS

  1. iHello Sir,

    I am SUMIT SHARMA B.E.(3rd year) from I.T.M. ,BHILWARA.I have some short tricks of maths which is very useful to solve multiplication easily & fastely.I am not saying that I can multiplying these nos. faster then calculater but I am also saying that I can solve them faster then a human.
    Sir, I have some problems & I want your help to solve these problem. The problem is that I don’t know that how many tricks are already discovered & which was not discovered by anyone.
    I want your help to give me the knowledge about that.

    I have short tricks for following destination :-

    1. SQUARE OF 1 TO 210.(DIFFERENT TRICKS FOR SQUARE OF 1 TO 99 & 100 TO 199)
    2. ANOTHER TRICKS TO SQUARE 100 TO 130, 200 TO 210,300 TO 310, 400 TO 410, 500 TO 510,600 TO 610, 700 TO710, 800 TO 810,900 TO 910,1000 TO 1130.
    3. ANOTHER TRICKS TO SQUARE 90 TO 100.
    4. TRICKS TO SQUARE OF 480 TO 500.
    5. TRICKS TO SQUARE OF 980 TO 1000.
    6. TRICKS TO SQUARE OF 1101 TO 1109.
    7. TRICKS TO SQUARE OF 1201 TO 1210,1301 TO 1310,1401TO 1410,1501 TO 1510 ,1601 TO 1610, 1701TO 1710, 1801 TO 1810,1901 TO 1910.
    8. TRICKS TO SQUARE OF 50 TO 59.
    9. TRICKS TO SQUARE OF “NO.WHO HAS LAST DIGIT 5”.
    10. QUBE OF 1 TO 15.
    11. QUBE OF 101 TO 110.
    12. MULTIPLYING ANY DIGIT BY 11,22,33,44,……99.
    13. MULTIPLYING ANY DIGIT BY 5.
    14. MULTIPLYING 2 DIGIT NO. BY 25.
    15. MULTIPLYING 2 DIGIT NO. BY 75.
    16. MULTIPLYING 2 DIGIT NO. BY 125.
    17. MULTIPLYING 2 DIGIT NO. BY 55.
    18. MULTIPLYING TWO 2 DIGIT NOS.
    19. ONE MORE TRICK TO MULTIPLY 75 .(BY THIS TRICK I CAN MULTIPLY ANY DIGIT NO. BY 75 ).

    Sir, please give the information about that.
    I am very grateful to you.
    Thanking you,
    Your faithfully,

    SUMIT SHARMA
    email address:- saurabhkumar4sharma@yahoo.com

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  4. hello,

    i m asmita..b.tech final year student……my project is based on vertically n croswise algorithm of the ancient indian vedic maths and embedding it in OLA and OLS methods for improved efficiency…at present i m coding vertically n crosswise algorithm….i m not able to code the carry save adder used……please do provide me some relevent information regarding above….it's quite urgent…plz do reply…

  5. The issue is , that though what Mr. Thapriyal has done is commendable- but most of the implementations are derived already from existing alternative computation methods given in the swami ji's book.

    The point is nothing beyond what is given in VM by swami ji has been done apart from some foreign authors.

    Vedic maths(VM) has to come out of ONLY FAST COMPUTATION paradigm only( DSP is an example of such an application)- as this makes it like any other system.

    More effort needs to go in doing fundamental research in the same- than using swami ji's idea and simply implementing the variants.

    This DEFINITELY DOES NOT help VM.

    regards,
    pankaj dhar

  6. Hello Sir
    I am Arushi Somani.I am doing M Tech in VLSI Design,from Institute of Technolgy & Management,Bhilwara(Raj.).MY thesis topic Based on Vedic Multiplier and work in Tanner Tool(Software).I am searching for Guide,how help me in my thesis.
    please give me the information about that.

    Thank You Sir
    Arushi

    MY ID is:- arushisomani@gmail.com

  7. Hello Sir,
    I am Arushi Somani,I am doing MTech in VLSI design,from Institute of Technology & Management,Bhilwara(Raj.).MY thesis topic based on Vedic Multiplier and working in Tanner Tool(Software).I am searching for guide,how help me in my thesis.
    please sir, give the information about that.

    Regards
    Arushi
    My id is- arushisomani@gmail.com

  8. Hello sir,
    I am Arjun.K.M.
    i am doing MS .This is a wonderful application of Vedic mathematics.This will create an awareness among the peoples of this generation to accept our heredity,means the discoveries in the ancient period .It will guide the knew generation to find their path……….I am interested to know more about its functioning

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